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Section 19 Serial I/O with FIFO
R01UH0134EJ0400 Rev. 4.00 Page 951 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit Bit Name
Initial
Value R/W Description
12 TDREQ 0 R Transmit Data Transfer Request
0: Indicates that the size of empty space in the transmit
FIFO is less than the size specified by the TFWM bit in
SIFCTR.
1: Indicates that the size of empty space in the transmit
FIFO is equal to or greater than the size specified by
the TFWM bit in SIFCTR.
A transmit data transfer request is issued when the empty
space in the transmit FIFO exceeds the size specified by
the TFWM bit in SIFCTR.
When transmit data is transferred through the direct
memory access controller, this bit is always cleared by an
access of the direct memory access controller. If the
condition for setting this bit is satisfied after the access of
the direct memory access controller, this module again
sets this bit to 1.
This bit is valid when the TXE bit in SICTR is 1.
If the size of empty space in the transmit FIFO is less
than the size specified by the TFWM bit in SIFCTR,
this module clears this bit.
11, 10 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
9 RFFUL 0 R Receive FIFO Full
0: Receive FIFO not full
1: Receive FIFO full
This bit is valid when the RXE bit in SICTR is 1.
If SIRDR is read, this module clears this bit.