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Section 19 Serial I/O with FIFO
R01UH0134EJ0400 Rev. 4.00 Page 949 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
19.3.4 Receive Data Register (SIRDR)
SIRDR reads receive data of this module. SIRDR stores data in the receive FIFO.
SIRDR is initialized by a receive reset caused by the RXRST bit in SICTR.
Bit:
Initial Value:
R/W:
Bit:
Initial Value:
R/W:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
16
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
RRRRRRRRRRRRRRRR
SIRDL[15:0]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
RRRRRRRRRRRRRRRR
SIRDR[15:0]
Bit Bit Name
Initial
Value R/W Description
31 to 16 SIRDL
[15:0]
Undefined R Left-Channel Receive Data
Store data received from the SIOFRxD pin as left-
channel data. The position of the left-channel data in
the receive frame is specified by the RDLA bit in
SIRDAR.
These bits are valid only when the RDLE bit in
SIRDAR is set to 1.
15 to 0 SIRDR
[15:0]
Undefined R Right-Channel Receive Data
Store data received from the SIOFRxD pin as right-
channel data. The position of the right-channel data in
the receive frame is specified by the RDRA bit in
SIRDAR.
These bits are valid only when the RDRE bit in
SIRDAR is set to 1.