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Section 37 Electrical Characteristics
R01UH0134EJ0400 Rev. 4.00 Page 1995 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Tc1 Tc2
Td1 Td2 Td3 Td4
Tr Tr w Tc3 Tc4 Tde
t
AD1
t
AD1
t
CSD1
t
AD1
t
AD1
t
AD1
t
AD1
t
RWD1
t
RWD1
t
CSD1
t
AD1
t
AD1
t
AD1
t
AD1
t
RDH2
t
RDS2
CKIO
A25 to A0
CSn
RD/WR
A12/A11
*
1
D15 to D0
t
RASD1
t
RASD1
RAS
Row
address
READ command
Column
address
Notes: 1. An address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn and TENDn is when active low is specified.
(1 to 4)
t
CASD1
t
CASD1
CAS
t
BSD
t
BSD
(High)
BS
CKE
t
DQMD1
t
DQMD1
DQMxx
t
DACD
t
DACD
DACKn
TENDn*
2
t
RDH2
t
RDS2
READA
command
Figure 37.20 Synchronous DRAM Burst Read Bus Cycle (Four Read Cycles)
(Auto Precharge, CAS Latency 2, WTRCD = 1 Cycle, WTRP = 0 Cycle)