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Section 16 Renesas Serial Peripheral Interface
Page 808 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
16.4 Operation
In this section, the serial transfer period means a period from the beginning of driving valid data to
the fetching of the final valid data.
16.4.1 Overview of Operations
This module is capable of serial transfers in slave mode and master mode. A particular mode of
this module can be selected by using the MSTR bit in the control register (SPCR). Table 16.4
gives the relationship between the modes and SPCR settings, and a description of each mode.
Table 16.4 Relationship between Modes and SPCR and Description of Each Mode
Mode Slave (SPI Operation) Master (SPI Operation)
MSTR bit setting 0 1
MODFEN bit setting 0 or 1 0
RSPCK signal Input Output
MOSI signal Input Output
MISO signal Output/Hi-Z Input
SSL signal Input Output
SSL polarity modification function Supported Supported
Transfer rate Up to B/8 Up to B/2
Clock source RSPCK input On-chip baud rate generator
Clock polarity Two Two
Clock phase Two Two
First transfer bit MSB/LSB MSB/LSB
Transfer data length 8 to 32 bits 8 to 32 bits
Burst transfer Possible (CPHA = 1) Possible (CPHA = 0,1)
RSPCK delay control Not supported Supported
SSL negation delay control Not supported Supported
Next-access delay control Not supported Supported
Transfer activation method SSL input active or RSPCK
oscillation
Transmit buffer is written when
SPE = 1
Sequence control Not supported Supported