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Section 27 Video Display Controller 3
R01UH0134EJ0400 Rev. 4.00 Page 1623 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
27.7.39 DE Area Size Register (DE_SIZE)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
0000000000000000
RRRRRRR/WR/WR/WR/WR/WR/WR/WR/WR/WR/W
0000000000000000
RRRRRR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/W
- - - - - - DE_HEIGHT[9:0]
- - - - - DE_WIDTH[10:0]
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
Bit Bit Name
Initial
Value R/W Description
31 to 26 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
25 to 16 DE_HEIGHT
[9:0]
H'000 R/W These bits specify the vertical length (height) of the
data enable (DE) signal area in number of lines.
15 to 11 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
10 to 0 DE_WIDTH
[10:0]
H'000 R/W These bits specify the horizontal length (width) of
the data enable (DE) signal area in number of
panel clock cycles.