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Section 20 Controller Area Network
R01UH0134EJ0400 Rev. 4.00 Page 1019 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit 11 — Timer Compare Match Interrupt 2 (IRR11): Indicates that a Compare-Match
condition occurred to the Timer Compare Match Register 2 (TCMR2). When the value set in the
TCMR2 matches to Cycle Time (TCMR2 = CYCTR), this bit is set.
Bit 11: IRR11 Description
0 Timer Compare Match has not occurred to the TCMR2 (initial value)
[Clearing condition] Writing 1
1 Timer Compare Match has occurred to the TCMR2
[Setting condition] TCMR2 matches to Cycle Time (TCMR2 = CYCTR)
Bit 10 — Start of new system matrix Interrupt (IRR10): Indicates that a new system matrix is
starting.
When CCR = 0, this bit is set at the successful completion of reception/transmission of time
reference message. Please note that when CMAX = 0 this interrupt is set at every basic cycle.
Bit 10: IRR10 Description
0 A new system matrix is not starting (initial value)
[Clearing condition] Writing 1
1 Cycle counter reached zero.
[Setting condition]
Reception/transmission of time reference message is successfully completed
when CMAX!= 3'b111 and CCR = 0
Bit 9 – Message Overrun/Overwrite Interrupt Flag (IRR9): Flag indicating that a message has
been received but the existing message in the matching Mailbox has not been read as the
corresponding RXPR or RFPR is already set to '1' and not yet cleared by the CPU. The received
message is either abandoned (overrun) or overwritten dependant upon the NMC (New Message
Control) bit. This bit is cleared when
all bit in UMSR (Unread Message Status Register) are cleared
(by writing
'1') or by setting MBIMR (MailBox interrupt Mast Register) for all UMSR flag set. It is also
cleared by writing a '1' to all the correspondent bit position in MBIMR. Writing to this bit position
has no effect.