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Page 2072 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
Item Page Revision (See Manual for Details)
11.8.2 Reset Start
Operation
616 Description amended
The output pins of this module (TIOC*) are initialized low
by a power-on reset and in deep standby mode.
13.5.6 Internal Reset in
Watchdog Timer Mode
674 Section added
15.1 Features 707,
708
Description amended
Clock synchronous serial communication: (SH7262:
channels 0 to 2, SH7264: channels 0 to 3)
...
In asynchronous mode, on-chip modem control
functions (RTS and CTS) (SH7262: channel 1, SH7264:
channels 1 and 3).
709 Description added
Figure 15.1 shows a block diagram. Note that some
channels do not have SCK, CTS and RTS pins.
15.3.5 Serial Mode Register
(SCSMR)
717 Table amended
Bit Bit Name
Initial
Value R/W Description
7 C/A 0 R/W Communication Mode
Selects operating mode from asynchronous and clock
synchronous modes. Clock synchronous mode cannot
be used by channels that do not have an SCK pin.
0: Asynchronous mode
1: Clock synchronous mode
15.3.6 Serial Control
Register (SCSCR)
723 Table amended
Bit Bit Name
Initial
Value
R/W Description
1, 0 CKE[1:0] 00 R/W Clock Enable
Select the clock source and enable or disable clock
output from the SCK pin. Depending on CKE[1:0], the
SCK pin can be used for serial clock output or serial
clock input. If serial clock output is set in clock
synchronous mode, set the C/A bit in SCSMR to 1, and
then set CKE[1:0]. Values other than B'00 cannot be
used for channels that do not have an SCK pin.
15.3.9 FIFO Control
Register (SCFCR)
740 Table amended
Bit Bit Name
Initial
Value
R/W Description
3 MCE 0 R/W Modem Control Enable
Enables modem control signals CTS and RTS.
0: Modem signal disabled*
1: Modem signal enabled
Note: * CTS is fixed at active 0 regardless of the input
value, and RTS is also fixed at 0.
The MCE bit should always be 0 for channels 0 and 2 to 7
on the SH7262, for channels 0, 2, and 4 to 7 on the
SH7264, and in clock synchronous mode.