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Section 25 NAND Flash Memory Controller
Page 1310 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit Bit Name
Initial
Value R/W Description
5 TRREQF0 0 R/(W)* FLDTFIFO Transfer Request Flag
Indicates that a transfer request is issued from
FLDTFIFO.
This bit is a flag. 1 cannot be written to this bit. Only 0
can be written to clear the flag.
0: Indicates that no transfer request is issued from
FLDTFIFO
1: Indicates that a transfer request is issued from
FLDTFIFO
4 STERINTE 0 R/W Interrupt Enable at Status Error
Enables or disables an interrupt request to the CPU
when a status error has occurred.
0: Disables the interrupt request to the CPU by a
status error
1: Enables the interrupt request to the CPU by a status
error
3 RBERINTE 0 RW Interrupt Enable at R/B Timeout Error
Enables or disables an interrupt request to the CPU
when a timeout error has occurred.
0: Disables the interrupt request to the CPU by an R/B
timeout error
1: Enables the interrupt request to the CPU by an R/B
timeout error
2 TEINTE 0 R/W Transfer End Interrupt Enable
Enables or disables an interrupt request to the CPU
when a transfer has been ended (TREND bit in
FLTRCR).
0: Disables the transfer end interrupt request to the
CPU
1: Enables the transfer end interrupt request to the
CPU