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Section 15 Serial Communication Interface with FIFO
Page 732 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
15.3.8 Bit Rate Register (SCBRR)
SCBRR is an 8-bit register that is used with the CKS1 and CKS0 bits in the serial mode register
(SCSMR) and the BGDM and ABCS bits in the serial extension mode register (SCEMR) to
determine the serial transmit/receive bit rate.
The CPU can always read and write to SCBRR. SCBRR is initialized to H'FF by a power-on reset.
Each channel has independent baud rate generator control, so different values can be set in eight
channels.
76543210
11111111
R/W R/W R/W R/W R/W R/W R/W R/W
Bit:
Initial value:
R/W:
The SCBRR setting is calculated as follows:
Asynchronous mode:
N =
N =
N =
N =
× 10
6
− 1 (Operation on a base clock with a frequency of 16 times
the bit rate)
× 10
6
− 1 (Operation on a base clock with a frequency of 8 times
the bit rate)
× 10
6
− 1 (Operation on a base clock with a frequency of 16 times
the bit rate)
× 10
6
− 1 (Operation on a base clock with a frequency of 8 times
the bit rate)
64 × 2
2n-1
× B
32 × 2
2n-1
× B
32 × 2
2n-1
× B
16 × 2
2n-1
× B
Pφ
Pφ
Pφ
Pφ
When baud rate generator operates in normal mode (when the BGDM bit of SCEMR is 0):
When baud rate generator operates in double speed mode (when the BGDM bit of
SCEMR is 1):