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Section 33 Power-Down Modes
Page 1794 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit Bit Name
Initial
Value R/W Description
2 VRAMWE2 1 R/W RAM Write Enable 2 (corresponding area: page 2* in
large-capacity on-chip RAM
0: Writing to page 2 is disabled.
1: Writing to page 2 is enabled.
1 VRAMWE1 1 R/W RAM Write Enable 1 (corresponding area: page 1* in
large-capacity on-chip RAM
0: Writing to page 1 is disabled.
1: Writing to page 1 is enabled.
0 VRAMWE0 1 R/W RAM Write Enable 0 (corresponding area: page 0* in
large-capacity on-chip RAM)
0: Writing to page 0 is disabled.
1: Writing to page 0 is enabled.
Note: * For addresses in each page, see section 31, On-Chip RAM.
33.2.14 System Control Register 5 (SYSCR5)
SYSCR5 is an 8-bit readable/writable register that enables or disables writing to a specified page
in the on-chip data-retention RAM.
When a RRAMWEn (n = 0 to 3) bit in SYSCR5 is set to 1, writing to page n is enabled. When a
RRAMWEn bit is cleared to 0, writing to page n is ignored. The initial value of a RRAMWEn bit
is 0.
SYSCR5 should be set with a program located in an area other than the on-chip data-retention
RAM.
SYSCR5 can be used only in 640-Kbyte version.
Note: When writing to this register, see section 33.4, Usage Notes.
76543210
Bit:
Initial value:
R/W:
00000000
R R R R R/W R/W R/W R/W
----
RRAM
WE3
RRAM
WE2
RRAM
WE0
RRAM
WE1