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Section 16 Renesas Serial Peripheral Interface
R01UH0134EJ0400 Rev. 4.00 Page 781 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
16.3.1 Control Register (SPCR)
SPCR sets the operating mode. If the MSTR and MODFEN bits are changed while the function of
this module is enabled by setting the SPE bit to 1, subsequent operations cannot be guaranteed.
76543210
Bit:
Initial value:
R/W:
00000000
R/W R/W R/W R/W R/W R/W R R
SPRIE SPE SPTIE SPEIE MSTR
MOD
FEN
⎯⎯
Bit Bit Name
Initial
Value R/W Description
7 SPRIE 0 R/W Receive Interrupt Enable
Enables or disables generation of receive interrupt
requests (SPRI) when the number of receive data
units in the receive buffer (SPRX) is equal to or
greater than the specified receive buffer data
triggering number and the SPRF flag in SPSR is set
to 1.
0: Disables the generation of receive interrupt
requests.
1: Enables the generation of receive interrupt
requests.
6 SPE 0 R/W Function Enable
Setting this bit to 1 enables the module function.
When the MODF bit in the status register (SPSR) is
1, the SPE bit cannot be set to 1 (see section 16.4.6,
Error Detection). Setting the SPE bit to 0 disables
the module function, and initializes a part of the
module function (see section 16.4.7, Initialization).
0: Disables the module function
1: Enables the module function