Filter
Top Products
Section 26 USB 2.0 Host/Function Module
R01UH0134EJ0400 Rev. 4.00 Page 1365 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
26.3.6 DMA-FIFO Bus Configuration Registers (D0FBCFG, D1FBCFG)
D0FBCFG is a register that controls DMA0-FIFO bus accesses. D1FBCFG is a register that
controls DMA1-FIFO bus accesses.
These registers are initialized by a power-on reset.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit:
Initial value:
R/W:
0000
Undefined Undefined Undefined Undefined Undefined Undefined Undefined
0
Undefined Undefined Undefined Undefined
RRRRRRRRRRRR/WRRRR
—— ———————TENDE — — — —
—
—
Bit Bit Name
Initial
Value R/W Description
15 to 12 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
11 to 5 Undefined R Reserved
The read value is undefined. The write value should
always be 0.
4 TENDE 0 R/W DMA Transfer End Sampling Enable
Controls acceptance of DMA transfer end signal
output from the direct memory access controller on
completion of a DMA transfer. For details, see
section 26.4.4 (3), DMA Transfers (D0FIFO/D1FIFO
Port).
0: DMA transfer end signal is not sampled.
1: DMA transfer end signal is sampled.
For a DMA transfer size of 16 bytes, clear the
TENDE bit to 0.
3 to 0 Undefined R Reserved
The read value is undefined. The write value should
always be 0.