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Page xxiv of xl R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
18.5.2 Note on Changing Mode from Master Transceiver to Master Receiver ........... 937
Section 19 Serial I/O with FIFO ........................................................................ 939
19.1 Features ............................................................................................................................. 939
19.2 Input/Output Pins .............................................................................................................. 941
19.3 Register Descriptions ........................................................................................................ 942
19.3.1 Mode Register (SIMDR) .................................................................................. 943
19.3.2 Control Register (SICTR) ................................................................................. 945
19.3.3 Transmit Data Register (SITDR) ...................................................................... 948
19.3.4 Receive Data Register (SIRDR) ....................................................................... 949
19.3.5 Status Register (SISTR) .................................................................................... 950
19.3.6 Interrupt Enable Register (SIIER) .................................................................... 955
19.3.7 FIFO Control Register (SIFCTR) ..................................................................... 957
19.3.8 Clock Select Register (SISCR) ......................................................................... 959
19.3.9 Transmit Data Assign Register (SITDAR) ....................................................... 960
19.3.10 Receive Data Assign Register (SIRDAR) ........................................................ 962
19.4 Operation .......................................................................................................................... 963
19.4.1 Serial Clocks ..................................................................................................... 963
19.4.2 Serial Timing .................................................................................................... 964
19.4.3 Transfer Data Format ........................................................................................ 965
19.4.4 Register Allocation of Transfer Data ................................................................ 966
19.4.5 FIFO .................................................................................................................. 968
19.4.6 Transmit and Receive Procedures ..................................................................... 970
19.4.7 Interrupts ........................................................................................................... 975
19.4.8 Transmit and Receive Timing ........................................................................... 977
Section 20 Controller Area Network ................................................................. 981
20.1 Summary ........................................................................................................................... 981
20.1.1 Overview .......................................................................................................... 981
20.1.2 Scope ................................................................................................................ 981
20.1.3 Audience ........................................................................................................... 981
20.1.4 References......................................................................................................... 981
20.1.5 Features ............................................................................................................. 982
20.2 Architecture ...................................................................................................................... 983
20.3 Programming Model - Overview ...................................................................................... 986
20.3.1 Memory Map .................................................................................................... 986
20.3.2 Mailbox Structure ............................................................................................. 988
20.3.3 Control Registers ............................................................................................ 1004
20.3.4 Mailbox Registers ........................................................................................... 1025
20.3.5 Timer Registers ............................................................................................... 1039