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Section 35 Motor Control PWM Timer
R01UH0134EJ0400 Rev. 4.00 Page 1837 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit Bit Name
Initial
Value R/W Description
15 to 13 Reserved
12 OTS 0 Output Terminal Select
Selects the pin used for PWM output. Unselected pins
output a low level (or a high level when the
corresponding bit in PWPR_n is set to 1). For details,
see table 35.3.
11, 10 Reserved
9 DT9 0 Duty
These bits specify the PWM output duty. A high level
(or a low level when the corresponding bit in PWPR_n
is set to 1) is output from the time PWCNT_n is cleared
by a PWCYR_n compare match until a PWDTR_n
compare match occurs. When all of the bits are 0, there
is no high-level (or low-level when the corresponding
bit in PWPR_n is set to 1) output period.
8 DT8 0
7 DT7 0
6 DT6 0
5 DT5 0
4 DT4 0
3 DT3 0
2 DT2 0
1 DT1 0
0 DT0 0
Table 35.3 Output Selection by OTS Bit
Register
Bit 12
Description OTS
PWDTR_1A/
PWDTR_2A
0 PWMnA output selected
1 PWMnB output selected
PWDTR_1C/
PWDTR_2C
0 PWMnC output selected
1 PWMnD output selected
PWDTR_1E/
PWDTR_2E
0 PWMnE output selected
1 PWMnF output selected
PWDTR_1G/
PWDTR_2G
0 PWMnG output selected
1 PWMnH output selected