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Section 9 Bus State Controller
Page 266 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit Bit Name
Initial
Value R/W Description
6 WM 0 R/W External Wait Mask Specification
Specifies whether or not the external wait input is
valid. The specification by this bit is valid even when
the number of access wait cycle is 0.
0: External wait input is valid
1: External wait input is ignored
5 to 0 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
CS4WCR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
0000000000000000
R R R R R R R R R R R/W R/W R R R/W R/W
0000010100000000
R R R R/W R/W R/W R/W R/W R/W R/W R R R R R/W R/W
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
----------BST[1:0] -- BW[1:0]
- - - SW[1:0] W[3:0] WM - - - - HW[1:0]
Bit Bit Name
Initial
Value R/W Description
31 to 22 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.