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Section 15 Serial Communication Interface with FIFO
R01UH0134EJ0400 Rev. 4.00 Page 759 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
In serial reception, this module operates as described below.
1. The transmission line is monitored, and if a 0 start bit is detected, internal synchronization is
performed and reception is started.
2. The received data is stored in SCRSR in LSB-to-MSB order.
3. The parity bit and stop bit are received.
After receiving these bits, this module carries out the following checks.
A. Stop bit check: Checks whether the stop bit is 1. If there are two stop bits, only the first is
checked.
B. Checks whether receive data can be transferred from the receive shift register (SCRSR) to
SCFRDR.
C. Overrun check: Checks that the ORER flag is 0, indicating that the overrun error has not
occurred.
D. Break check: Checks that the BRK flag is 0, indicating that the break state is not set.
If all the above checks are passed, the receive data is stored in SCFRDR.
Note: When a parity error or a framing error occurs, reception is not suspended.
4. If the RIE bit in SCSCR is set to 1 when the RDF or DR flag changes to 1, a receive-FIFO-
data-full interrupt (RXI) request is generated. If the RIE bit or the REIE bit in SCSCR is set to
1 when the ER flag changes to 1, a receive-error interrupt (ERI) request is generated. If the
RIE bit or the REIE bit in SCSCR is set to 1 when the BRK or ORER flag changes to 1, a
break reception interrupt (BRI) request is generated.