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Section 31 On-Chip RAM
R01UH0134EJ0400 Rev. 4.00 Page 1673 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Ports
Each page of the on-chip high-speed RAM has two independent read and write ports and is
connected to the internal DMA bus (ID bus), CPU instruction fetch bus (F bus), and CPU
memory access bus (M bus). (Note that the F bus is connected only to the read ports.)
The F bus and M bus are used for access by the CPU, and the ID bus is used for access by the
direct memory access controller.
Each page of the on-chip large-capacity RAM has one read and write port and is connected to
the internal CPU bus (IC bus), internal DMA bus (ID bus) and internal graphic buses 1 to 4
(IV1 to IV4). For 1-Mbyte version, pages 0 and 1 of the on-chip RAM for data retention are
included in page 5 of the on-chip large-capacity RAM. Accordingly, pages 0 and 1 of the on-
chip RAM for data retention are shared with the read and write port of page 5 of the on-chip
large-capacity RAM. On the other hand, since the on-chip RAM for data retention is included
in page 0 to 2 for 640-Kbyte version, it is shared with the read and write port of the same
pages.
Priority
When the same page of the on-chip high-speed RAM is accessed from different buses
simultaneously, the access is processed according to the priority. The priority is ID bus M
bus F bus.
When the same page of the on-chip large-capacity RAM is accessed from different buses
simultaneously, the access is processed according to the priority. The priority is IV1 bus IV2
bus IV3 bus IV4 bus IC bus (when the IC bus does not have the bus mastership in the
preceding bus cycle) ID bus IC bus (when the IC bus has the bus mastership in the
preceding bus cycle)
Number of access cycles
On-chip high-speed RAM: the number of cycles for access to read or write from buses F and I
is one cycle of I. Number of cycles for access from the ID bus
depend on the ratio of the CPU clock (I) to the bus clock (B).
Table 31.6 indicates number of cycles for access from the ID bus.