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Section 22 Renesas SPDIF Interface
R01UH0134EJ0400 Rev. 4.00 Page 1187 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
where M = receive margin
N = oversampling rate
L = frame length = 33
D = duty cycle = 0.6
F = oversampling clock deviation = Level II accuracy = 1000 in 10e
–6
Figure 22.7 indicates what the receive margin M represents
Internal Clock
Data
M
Sampling Clock
Figure 22.7 Receive Margin
Introducing jitter into the equation gives the following inequality.
j
≤ 0.5 − − (L − 0.5) F − (1 + F) × 100%
1
2N
D − 0.5
N
J = clock jitter
Eight times oversampling produces a receive margin = 39.25%
Four times oversampling produces a receive margin = 31.75%
Two times oversampling produces a receive margin = 16.75%
The fastest sample frequency is 48 kHz. This requires a clock speed of 128 48 kHz = 6.144
MHz. The worst case jitter in one cycle is specified at 40 ns = 24.5% of the period. This means
that an oversampling rate of 4 or more will satisfy the inequality and therefore be sufficient for
clock recovery.