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Section 20 Controller Area Network
R01UH0134EJ0400 Rev. 4.00 Page 1043 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit 10 to 8 — Cycle Count Maximum (CMAX): Indicates the maximum number of CCR. The
number of basic cycles available in the matrix cycle for Timer Triggered transmission is (Cycle
Count Maximum + 1).
Unless CMAX = 3'b111, this module is in time-trigger mode and time trigger function is
available. If CMAX = 3'b111, this module is in event-trigger mode.
Bit[10:8]: CMAX[2:0] Description
0 0 0 Cycle Count Maximum = 0
0 0 1 Cycle Count Maximum = 1
0 1 0 Cycle Count Maximum = 3
0 1 1 Cycle Count Maximum = 7
1 0 0 Cycle Count Maximum = 15
1 0 1 Cycle Count Maximum = 31
1 1 0 Cycle Count Maximum = 63
1 1 1 CCR is cleared and this module is in event-trigger mode. (initial value)
Important: Please set CMAX = 3'b111 when event-trigger mode is used.
Bits 7 to 4: Reserved. The written value should always be '0' and the returned value is ‘0’.
Bit 3 to 0 — Tx-Enable Window (TEW): Indicates the width of Tx-Enable Window. TEW =
H'00 shows the width is one nominal Bit Timing. All values from 0 to 15 are allowed to be set.
Bit[3:0]: TEW[3:0] Description
0 0 0 0 The width of Tx-Enable Window = 1 (initial value)
0 0 0 1 The width of Tx-Enable Window = 2
0 0 1 0 The width of Tx-Enable Window = 3
0 0 1 1 The width of Tx-Enable Window = 4
. . . . . . . . . .
. . . . . . . . . .
1 1 1 1 The width of Tx-Enable Window = 16
Note: The CAN core always needs a time between 1 to 2 bit timing to initiate transmission. The
above values are not considering this accuracy.