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Section 31 On-Chip RAM
Page 1676 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
31.2.3 Data Retention
Data in the on-chip high-speed RAM and the large-capacity RAM (including on-chip data
retention RAM) are retained in the states other than power-on reset and deep standby mode. In
power-on reset and deep standby mode, these RAMs operate as described below.
(1) Power-on Reset
(a) On-Chip High-Speed RAM
Data are retained on a power-on reset by disabling the setting of either the RAME or RAMWE bit.
Data are not retained when the setting of the RAME and RAMWE bits are both enabled.
(b) On-Chip Large-Capacity RAM (Excluding On-Chip Data Retention RAM)
Data are retained on a power-on reset by disabling the setting of either the VRAME or VRAMWE
bit.
Data are not retained when the setting of the VRAME and VRAMWE bits are both enabled.
(c) On-Chip Data Retention RAM
Data are retained on a power-on reset by disabling the setting of any of the VRAME, VRAMWE,
or RRAMWE, excluding the case that deep standby mode is canceled by power-on reset.
Data are not retained when the setting of the VRAME, VRAMWE and RRAMWE bits are all
enabled.
(2) Deep Standby Mode
(a) On-Chip High-Speed RAM and On-Chip Large-Capacity RAM (Excluding On-Chip
Data Retention RAM)
Data are not retained.
(b) On-Chip Data Retention RAM
Data are retained in deep standby mode by enabling the setting of the RRAMKP bit, excluding the
case that deep standby mode is canceled by power-on reset. In the case that deep standby mode is
canceled by interrupt or pins for cancelling, power-on reset exception handling is executed, but the
data are retained.