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Section 20 Controller Area Network
Page 1050 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
Timer Clear-Set:
The Timer value can only be cleared when a Compare Match occurs if it is enabled by the Bit6 in
the TTCR0. TCMR1 and TCMR2 do not have this function.
Cancellation of the messages in the transmission queue:
The messages in the transmission queue can only be cleared by the TCMR2 through setting TXCR
when a Compare Match occurs while this module is not in the halt status. TCMR1 and TCMR0 do
not have this function.
TCMR0 (Address = H'098)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Bit:
Initial value:
R/W:
1111111111111111
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
TCMR0[15:0]
Bit 15 to 0 — Timer Compare Match Register (TCMR0): Indicates the value of TCNTR when
compare match occurs.
TCMR1 (Address = H'09C)
1514131211109876543210
1111111111111111
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
TCMR1[15:0]
Bit:
Initial value:
R/W:
Bit 15 to 0 — Timer Compare Match Register (TCMR1): Indicates the value of CYCTR when
compare match occurs.
TCMR2 (Address = H'0A0)
1514131211109876543210
1111111111111111
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
TCMR2[15:0]
Bit:
Initial value:
R/W:
Bit 15 to 0 — Timer Compare Match Register (TCMR2): Indicates the value of CYCTR when
compare match occurs.