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Section 36 List of Registers
Page 1922 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
Module Name
Register
Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0
Controller area
network
MBn_CONTROL
0_L_0
(n = 0 to 31)
EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[8]
EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] EXTID[0]
MBn_LAFM0_0
(n = 0 to 31)*
1
STDID_
LAFM[10]
STDID_
LAFM[9]
STDID_
LAFM[8]
STDID_
LAFM[7]
STDID_
LAFM[6]
STDID_
LAFM[5]
STDID_
LAFM[4]
STDID_
LAFM[3]
STDID_
LAFM[2]
STDID_
LAFM[1]
STDID_
LAFM[0]
IDE EXTID_
LAFM[17]
EXTID_
LAFM[16]
MBn_LAFM0_0
(n = 0 to 31)*
2
IDE STDID_
LAFM[10]
STDID_
LAFM[9]
STDID_
LAFM[8]
STDID_
LAFM[7]
STDID_
LAFM[6]
STDID_
LAFM[5]
STDID_
LAFM[4]
STDID_
LAFM[3]
STDID_
LAFM[2]
STDID_
LAFM[1]
STDID_
LAFM[0]
EXTID_
LAFM[17]
EXTID_
LAFM[16]
MBn_LAFM1_0
(n = 0 to 31)
EXTID_
LAFM[15]
EXTID_
LAFM[14]
EXTID
_LAFM[13]
EXTID_
LAFM[12]
EXTID_
LAFM[11]
EXTID_
LAFM[10]
EXTID_
LAFM[9]
EXTID_
LAFM[8]
EXTID_
LAFM[7]
EXTID_
LAFM[6]
EXTID_
LAFM[5]
EXTID_
LAFM[4]
EXTID_
LAFM[3]
EXTID_
LAFM[2]
EXTID_
LAFM[1]
EXTID_
LAFM [0]
MBn_DATA_01_
0 (n = 0 to 31)
MSG_DATA0 MSG_DATA0 MSG_DATA0 MSG_DATA0 MSG_DATA0 MSG_DATA0 MSG_DATA0 MSG_DATA0
MSG_DATA1 MSG_DATA1 MSG_DATA1 MSG_DATA1 MSG_DATA1 MSG_DATA1 MSG_DATA1 MSG_DATA1
MBn_DATA_23_
0 (n = 0 to 31)
MSG_DATA2 MSG_DATA2 MSG_DATA2 MSG_DATA2 MSG_DATA2 MSG_DATA2 MSG_DATA2 MSG_DATA2
MSG_DATA3 MSG_DATA3 MSG_DATA3 MSG_DATA3 MSG_DATA3 MSG_DATA3 MSG_DATA3 MSG_DATA3
MBn_DATA_45_
0 (n = 0 to 31)
MSG_DATA4 MSG_DATA4 MSG_DATA4 MSG_DATA4 MSG_DATA4 MSG_DATA4 MSG_DATA4 MSG_DATA4
MSG_DATA5 MSG_DATA5 MSG_DATA5 MSG_DATA5 MSG_DATA5 MSG_DATA5 MSG_DATA5 MSG_DATA5
MBn_DATA_67_
0 (n = 0 to 31)
MSG_DATA6 MSG_DATA6 MSG_DATA6 MSG_DATA6 MSG_DATA6 MSG_DATA6 MSG_DATA6 MSG_DATA6
MSG_DATA7 MSG_DATA7 MSG_DATA7 MSG_DATA7 MSG_DATA7 MSG_DATA7 MSG_DATA7 MSG_DATA7
MBn_CONTROL
1_0 (n =0)
NMC MBC[2] MBC[1] MBC[0]
DLC[3] DLC[2] DLC[1] DLC[0]
MBn_CONTROL
1_0 (n = 0 to 31)
NMC ATX DART MBC[2] MBC[1] MBC[0]
DLC[3] DLC[2] DLC[1] DLC[0]
MBn_TIMESTA
MP_0 (n = 0 to
15, 30, 31)
TS15 TS14 TS13 TS12 TS11 TS10 TS9 TS8
TS7 TS6 TS5 TS4 TS3 TS2 TS1 TS0
MBn_TTT_0
(n = 24 to 30)
TTT15 TTT14 TTT13 TTT12 TTT11 TTT10 TTT9 TTT8
TTT7 TTT6 TTT5 TTT4 TTT3 TTT2 TTT1 TTT0