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Section 16 Renesas Serial Peripheral Interface
R01UH0134EJ0400 Rev. 4.00 Page 841 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
(2) Slave Mode Operation
(a) Starting Serial Transfer
If this module detects an SSL input signal assertion when the CPHA bit in the command register 0
(SPCMD0) is 0, this module is required to start driving valid data to the MISO output signal. For
this reason, when the CPHA bit is 0, the asserting of the SSL input signal triggers the start of a
serial transfer.
If this module detects the first RSPCK edge in an SSL signal asserted condition when the CPHA
bit is 1, this module is required to start driving valid data to the MISO output signal. For this
reason, when the CPHA bit is 1, the first RSPCK edge in an SSL signal asserted condition triggers
the start of a serial transfer.
When detecting the start of a serial transfer in a condition in which the shift register is empty, this
module changes the status of the shift register to "full", so that data cannot be copied from the
transmit buffer to the shift register when serial transfer is in progress. If the shift register was full
before the serial transfer started, this module leaves the status of the shift register intact, in the full
state.
Irrespective of CPHA bit settings, this module starts driving MISO output signals at the SSL
signal assertion timing. Whether the data output from this module is valid or invalid differs
depending on CPHA bit settings.
For details on the transfer format, see section 16.4.4, Transfer Format. The polarity of the SSL
input signal depends on the setting of the SSL0P bit in the slave select polarity register (SSLP).