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Section 37 Electrical Characteristics
R01UH0134EJ0400 Rev. 4.00 Page 1989 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Read
Note: * The waveform for DACKn and TENDn is when active low is specified.
Write
Th
t
AD1
t
RSD
t
RSD
t
RDS1
t
CSD1
t
RWD1
T1 TwxT2 Tf
t
WDD1
t
BSD
t
WDH1
t
RDH1
t
AD1
t
CSD1
CKIO
A25 to A0
CSn
WEn
RD
D15 to D0
D15 to D0
RD/WR
RD/WR
BS
WAIT
DACKn
TENDn*
t
DACD
t
DACD
t
BSD
t
WTS
t
WTS
t
RWD1
t
RWD1
t
RWD1
t
WED1
t
WED1
t
WTH
t
WTH
Figure 37.14 Bus Cycle of SRAM with Byte Selection (SW = 1 Cycle, HW = 1 Cycle,
One Asynchronous External Wait Cycle, BAS = 0 (Write Cycle UB/LB Control))