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R01UH0134EJ0400 Rev. 4.00 Page xxi of xl
Sep 24, 2014
Section 15 Serial Communication Interface with FIFO .................................... 707
15.1 Features ............................................................................................................................. 707
15.2 Input/Output Pins .............................................................................................................. 710
15.3 Register Descriptions ........................................................................................................ 711
15.3.1 Receive Shift Register (SCRSR) ....................................................................... 715
15.3.2 Receive FIFO Data Register (SCFRDR) .......................................................... 715
15.3.3 Transmit Shift Register (SCTSR) ..................................................................... 716
15.3.4 Transmit FIFO Data Register (SCFTDR) ......................................................... 716
15.3.5 Serial Mode Register (SCSMR) ........................................................................ 717
15.3.6 Serial Control Register (SCSCR) ...................................................................... 720
15.3.7 Serial Status Register (SCFSR) ........................................................................ 724
15.3.8 Bit Rate Register (SCBRR) .............................................................................. 732
15.3.9 FIFO Control Register (SCFCR) ...................................................................... 738
15.3.10 FIFO Data Count Set Register (SCFDR) .......................................................... 741
15.3.11 Serial Port Register (SCSPTR) ......................................................................... 742
15.3.12 Line Status Register (SCLSR) .......................................................................... 745
15.3.13 Serial Extension Mode Register (SCEMR) ....................................................... 746
15.4 Operation .......................................................................................................................... 747
15.4.1 Overview ........................................................................................................... 747
15.4.2 Operation in Asynchronous Mode .................................................................... 750
15.4.3 Operation in Clock Synchronous Mode ............................................................ 761
15.5 Interrupts ........................................................................................................................... 770
15.6 Usage Notes ...................................................................................................................... 771
15.6.1 SCFTDR Writing and TDFE Flag .................................................................... 771
15.6.2 SCFRDR Reading and RDF Flag ..................................................................... 771
15.6.3 Restriction on Direct Memory Controller Usage .............................................. 772
15.6.4 Break Detection and Processing ....................................................................... 772
15.6.5 Sending a Break Signal ..................................................................................... 772
15.6.6 Receive Data Sampling Timing and Receive Margin
(Asynchronous Mode) ...................................................................................... 772
15.6.7 Selection of Base Clock in Asynchronous Mode .............................................. 774
Section 16 Renesas Serial Peripheral Interface ................................................. 775
16.1 Features ............................................................................................................................. 775
16.2 Input/Output Pins .............................................................................................................. 778
16.3 Register Descriptions ........................................................................................................ 779
16.3.1 Control Register (SPCR) ................................................................................... 781
16.3.2 Slave Select Polarity Register (SSLP) .............................................................. 783
16.3.3 Pin Control Register (SPPCR) .......................................................................... 784
16.3.4 Status Register (SPSR) ..................................................................................... 786