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Section 6 Exception Handling
R01UH0134EJ0400 Rev. 4.00 Page 153 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
6.9 Usage Notes
6.9.1 Value of Stack Pointer (SP)
The value of the stack pointer must always be a multiple of four. If it is not, an address error will
occur when the stack is accessed during exception handling.
6.9.2 Value of Vector Base Register (VBR)
The value of the vector base register must always be a multiple of four. If it is not, an address error
will occur when the stack is accessed during exception handling.
6.9.3 Address Errors Caused by Stacking of Address Error Exception Handling
When the stack pointer is not a multiple of four, an address error will occur during stacking of the
exception handling (interrupts, etc.) and address error exception handling will start up as soon as
the first exception handling is ended. Address errors will then also occur in the stacking for this
address error exception handling. To ensure that address error exception handling does not go into
an endless loop, no address errors are accepted at that point. This allows program control to be
shifted to the address error exception service routine and enables error processing.
When an address error occurs during exception handling stacking, the stacking bus cycle (write) is
executed. During stacking of the status register (SR) and program counter (PC), the SP is
decremented by 4 for both, so the value of SP will not be a multiple of four after the stacking
either. The address value output during stacking is the SP value, so the address where the error
occurred is itself output. This means the write data stacked will be undefined.
6.9.4 Interrupt Control via Modification of Interrupt Mask Bits
When enabling interrupts by changing the Interrupt Mask bits (I3-I0) of the Status Register (SR)
using the LDC or LDC.L instructions, interrupts might not be accepted during the execution of the
5 instructions immediately after the LDC/LDC.L instruction.
Therefore, when enabling/disabling interrupts by changing the Interrupt Mask bits (I3-I0) of the
Status Register (SR) using LDC/LDC.L instructions, please place at least 5 instructions between
the interrupt-enable instruction and the interrupt-disable instruction.