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Section 8 Cache
Page 226 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
(2) Data Array Write
The longword data specified by the data is written to the position specified by the L bit in the
address from the entry address specified by the address and the entry corresponding to the way.
31 23 22 13 12 11
31 29 28
10 43210
111100000
111100000
111100010
*----------*
*----------*
*----------*
*----------*
*----------*
*----------*
W
*
LRU XX000 X V
E
00
0
31 23 22 13 12 11 10 4 3 2 1 0
31 0
W
0L 0
31 23 22 13 12 11 10
11 10 9
43210
43210
W
*A00
31 23 22 13 12 11
31 29 28
10 43210
111100001
111100001
111100011
W
*
LRU XX000 U V
E
00
0
31 23 22 13 12 11 10 4 3 2 1 0
31 0
W
0L 0
31 23 22 13 12 11 10
11 10 9
43210
43210
W
*A00
1. Instruction cache
1.1 Address array access
(a) Address specification
Read access
Write access
(b) Data specification (both read and write accesses)
1.2 Data array access (both read and write accesses)
(a) Address specification
Tag address (28 to 11)
Entry address
(b) Data specification
Longword data
*: Don't care
E: Bit 10 of entry address for read, don't care for write
X: 0 for read, don't care for write
[Legend]
Entry address
Tag address (28 to 11)
Entry address
Entry address
Entry address
Entry address
Longword data
2.2 Data array access (both read and write accesses)
(a) Address specification
(b) Data specification
2. Operand cache
2.1 Address array access
(a) Address specification
Read access
Write access
(b) Data specification (both read and write accesses)
Figure 8.4 Specifying Address and Data for Memory-Mapped Cache Access