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Section 1 Overview
Page 4 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
Items Specification
Bus state controller
Address space divided into seven areas (0 to 6), each a maximum of
64 Mbytes
The following features settable for each area independently
Bus size (8 or 16 bits): Available sizes depend on the area.
Number of access wait cycles (different wait cycles can be
specified for read and write access cycles in some areas)
Idle wait cycle insertion (between the same area access cycles or
different area access cycles)
Specifying the memory to be connected to each area enables
direct connection to SRAM, SRAM with byte selection, SDRAM,
and burst ROM (clocked synchronous or asynchronous). The
address/data multiplexed I/O (MPX) interface are also available.
PCMCIA interface
Outputs a chip select signal (CS0 to CS6) according to the target
area (CS assert or negate timing can be selected by software)
SDRAM refresh
Auto refresh or self refresh mode selectable
SDRAM burst access
Direct memory access
controller
Sixteen channels; external requests are available for one of them in
the SH7262 Group, and for two of them in the SH7264 Group.
Can be activated by on-chip peripheral modules
Burst mode and cycle steal mode
Intermittent mode available (16 and 64 cycles supported)
Transfer information can be automatically reloaded
Clock pulse generator
Clock mode: Input clock can be selected from external input (EXTAL
or USB_X1) or crystal resonator
Input clock can be multiplied by 12 (max.) by the internal PLL circuit
Three types of clocks generated:
CPU clock: Maximum 144 MHz
Bus clock: Maximum 72 MHz
Peripheral clock: Maximum 36 MHz
Watchdog timer
On-chip one-channel watchdog timer
A counter overflow can reset the LSI