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Section 9 Bus State Controller
R01UH0134EJ0400 Rev. 4.00 Page 291 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
9.5 Operation
9.5.1 Endian/Access Size and Data Alignment
This LSI supports both big endian, in which the most significant byte (MSB) of data is that in the
direction of the 0th address, and little endian, in which the least significant byte (LSB) is that in
the direction of the 0th address. In the initial state after a power-on reset, all areas will be in big
endian mode. Endian mode can be changed by setting the CSnBCR register as long as the target
space is not being accessed.
Data bus width can be selected from 8 bits and 16 bits for the normal memory and SRAM with
byte selection. It is fixed to 16 bits for SDRAM. Two data bus widths (8 bits and 16 bits) are
available for the PCMCIA interface. For MPX-I/O, the data bus width is fixed to either 8 or 16
bits, or made selectable as 8 bits or 16 bits by one of the address lines.
Endian specification and data bus width varies depending on boot mode. For details, refer to
section 9.3.2, Data Bus Width and Endian Specification for Each Area Depending on Boot Mode.
Data alignment is performed in accordance with the data bus width selected for the device. This
also means that four read operations are required to read longword data from a byte-width device.
In this LSI, data alignment and conversion of data length is performed automatically between the
respective interfaces.
Tables 9.5 to 9.8 show the relationship between device data width and access unit. Note that the
correspondence between addresses and strobe signals for the 16-bit bus width depends on the
endian setting. For example, with big endian and a 16-bit bus width, WE1 corresponds to the 0th
address, which is represented by WE0 when little endian has been selected.
Since instructions are fetched with both 32- and 16-bit accesses, their alignment in the little-endian
area is difficult. Execute instructions from big-endian area.