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Section 27 Video Display Controller 3
Page 1592 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
Reference Hsync
Vsync for video
VIDEO_DISP_WIDTH
VIDEO_DISP_HEIGHT
Video data
1
VIDEO_DISP_HSTART + 16
Figure 27.17 Settings for Video Data Reading (from Memory)
27.7.15 Horizontal Video Display Position Register (VIDEO_DISP_HSTART)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
0000000000000000
RRRRRRRRRRRRRRRR
0000000000000000
R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
------
-
----------
- - - - - VIDEO_DISP_HSTART[9:0]
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
Bit Bit Name
Initial
Value R/W Description
31 to 10 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
9 to 0 VIDEO_DISP_
HSTART [9:0]
H'000 R/W These bits specify in number of pixels the
horizontal start position of the video data to be
read in the video display mode.