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Section 26 USB 2.0 Host/Function Module
R01UH0134EJ0400 Rev. 4.00 Page 1345 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
(8) Other Features
Transfer ending function using transaction count
BRDY interrupt event notification timing change function (BFRE)
Function that automatically clears the buffer memory after the data for the pipe specified at the
DnFIFO (n = 0 or 1) port has been read (DCLRM)
NAK setting function for response PID generated by end of transfer (SHTNAK)
26.2 Input/Output Pins
Table 26.1 shows the pin configuration of the USB.
Table 26.1 USB Pin Configuration
Category Name Pin Name I/O Function
USB bus
interface
USB D+ data DP I/O D+ I/O of the USB on-chip transceiver
This pin should be connected to the D+ pin of
the USB bus.
USB D- data DM I/O D I/O of the USB on-chip transceiver
This pin should be connected to the D- pin of
the USB bus.
VBUS
monitor
input
VBUS input VBUS Input USB cable connection monitor pin
This pin should be connected directly to the
VBUS of the USB bus. Whether the VBUS is
connected or disconnected can be detected.
If this pin is not connected with the VBUS of
the USB bus, it should be supplied with 5 V. It
should be supplied with 5 V also when the
host controller function is selected.
Note: The VBUS cannot be supplied to
connected peripheral devices.
Reference
resistor
Reference input REFRIN Input Reference resistor connection pin
This pin should be connected to USBAPVss
through a 5.6 k 1% resistor.
Clock Crystal resonator
for USB/external
clock
USB_X1 Input This pin should be connected to crystal
resonator for the USB. This pin can also be
used for external clock input.
USB_X2 Output