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Section 5 Clock Pulse Generator
R01UH0134EJ0400 Rev. 4.00 Page 115 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Section 5 Clock Pulse Generator
This LSI has a clock pulse generator that generates a CPU clock (I), a peripheral clock (P), and
a bus clock (B). The clock pulse generator consists of a crystal oscillator, PLL circuits, and
divider circuits.
5.1 Features
Four clock operating modes
The mode is selected from among the four clock operating modes based on the frequency
range to be used and the input clock type: the clock from crystal resonator or the clock for
USB 2.0 host/function module.
Three clocks generated independently
A CPU clock (I) for the CPU and cache; a peripheral clock (P) for the on-chip peripheral
modules; a bus clock (B = CKIO) for the external bus interface
Frequency change function
CPU and peripheral clock frequencies can be changed independently using the PLL (phase
locked loop) circuits and divider circuits within this module. Frequencies are changed by
software using frequency control register (FRQCR) settings.
Power-down mode control
The clock can be stopped in sleep mode, software standby mode, and deep standby mode, and
specific modules can be stopped using the module standby function. For details on clock
control in the power-down modes, see section 33, Power-Down Modes.