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Section 2 CPU
R01UH0134EJ0400 Rev. 4.00 Page 83 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
2.4.5 Shift Instructions
Table 2.14 Shift Instructions
Instruction Instruction Code Operation
Execu-
tion
Cycles
T Bit
Compatibility
SH2,
SH2E
SH4 SH-2A
ROTL Rn 0100nnnn00000100 T Rn MSB 1 MSB Yes Yes Yes
ROTR Rn 0100nnnn00000101 LSB Rn T 1 LSB Yes Yes Yes
ROTCL Rn 0100nnnn00100100 T Rn T 1 MSB Yes Yes Yes
ROTCR Rn 0100nnnn00100101 T Rn T 1 LSB Yes Yes Yes
SHAD Rm,Rn 0100nnnnmmmm1100 When Rm 0, Rn << Rm Rn
When Rm < 0, Rn >> |Rm|
[MSB Rn]
1 Yes Yes
SHAL Rn 0100nnnn00100000 T Rn 0 1 MSB Yes Yes Yes
SHAR Rn 0100nnnn00100001 MSB Rn T 1 LSB Yes Yes Yes
SHLD Rm,Rn 0100nnnnmmmm1101 When Rm 0, Rn << Rm Rn
When Rm < 0, Rn >> |Rm|
[0 Rn]
1 Yes Yes
SHLL Rn 0100nnnn00000000 T Rn 0 1 MSB Yes Yes Yes
SHLR Rn 0100nnnn00000001 0 Rn T 1 LSB Yes Yes Yes
SHLL2 Rn 0100nnnn00001000 Rn << 2 Rn 1 Yes Yes Yes
SHLR2 Rn 0100nnnn00001001 Rn >> 2 Rn 1 Yes Yes Yes
SHLL8 Rn 0100nnnn00011000 Rn << 8 Rn 1 Yes Yes Yes
SHLR8 Rn 0100nnnn00011001 Rn >> 8 Rn 1 Yes Yes Yes
SHLL16 Rn 0100nnnn00101000 Rn << 16 Rn 1 Yes Yes Yes
SHLR16 Rn 0100nnnn00101001 Rn >> 16 Rn 1 Yes Yes Yes