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Section 23 CD-ROM Decoder
Page 1210 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit Bit Name
Initial
Value R/W Description
1 ST_SECS 0 R Indicates that a sector has been processed as a short
sector with the aid of interpolated sync codes. If this bit
is set to 1, stop decoding immediately and retry the
procedure starting from the sector prior to the currently
being decoded sector.
0 ST_SECL 0 R Indicates that a sector has been processed as a long
sector with the aid of interpolated sync codes. If this bit
is set to 1, stop decoding immediately and retry the
procedure starting from two sectors prior to the sector
currently being decoded.
23.3.9 Post-ECC Header Error Status Register (CROMST1)
The post-ECC header error status register (CROMST1) indicates error status in the post-ECC
header.
76543210
00000000
RRRRRRRR
Bit:
Initial value:
R/W:
----
ER2_
HEAD0
ER2_
HEAD1
ER2_
HEAD2
ER2_
HEAD3
Bit Bit Name
Initial
Value R/W Description
7 to 4 All 0 R Reserved
These bits are always read as 0 and cannot be
modified.
3 ER2_
HEAD0
0 R Indicates an error in the minutes field of the header
after ECC correction.
2 ER2_
HEAD1
0 R Indicates an error status in the seconds field of the
header after ECC correction.
1 ER2_
HEAD2
0 R Indicates an error in the frames (1/75 second) field of
the header after ECC correction.
0 ER2_
HEAD3
0 R Indicates an error in the mode field of the header after
ECC correction.