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Section 16 Renesas Serial Peripheral Interface
Page 830 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
The operation of the flags at the timing shown in steps (1) to (4) in the figure is described below.
1. If a serial transfer terminates when the receive buffer does not have a space for the receive data
length, this module detects an overrun error, and sets the OVRF bit to 1. This module does not
copy the data in the shift register to the receive buffer.
2. The OVFR bit is not cleared even when SPDR is read and thus the number of data bytes in the
receive buffer becomes less than the number of the receive buffer data triggering number
specified by the RXTRG bits.
3. If the serial transfer terminates in an overrun error state, this module determines that the shift
register is empty; in this manner, data transfer is enabled from the transmit buffer to the shift
register.
4. If 0 is written to the OVRF bit after SPSR is read with OVRF = 1, this module clears the
OVRF bit.
The occurrence of an overrun can be checked either by reading SPSR or by using an error
interrupt and reading SPSR. When using an error interrupt, set the SPEIE bit in the control register
(SPCR) to 1. When executing a serial transfer without using an error interrupt, measures should be
taken to ensure the early detection of overrun errors, such as reading SPSR immediately after
SPDR is read.
The OVRF bit is cleared to 0 under the following conditions:
After SPSR is read in a condition in which the OVRF bit is set to 1, 0 is written to the OVRF
bit.
Power-on reset
Note: When the receive buffer has area enough to store receive data with an overrun error, this
module receives receive data.