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Section 12 Compare Match Timer
Page 652 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
12.2.2 Compare Match Timer Control/Status Register (CMCSR)
CMCSR is a 16-bit register that indicates compare match generation, enables or disables
interrupts, and selects the counter input clock.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0000000000000000
R R R R R R R R R/(W)* R/W R R R R R/W R/W
Bit:
Initial value:
R/W:
- - - - - - - - CMF CMIE - - - - CKS[1:0]
Bit Bit Name
Initial
Value R/W Description
15 to 8 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
7 CMF 0 R/(W)* Compare Match Flag
Indicates whether or not the values of CMCNT and
CMCOR match.
0: CMCNT and CMCOR values do not match
[Clearing condition]
When 0 is written to CMF after reading CMF = 1
1: CMCNT and CMCOR values match
6 CMIE 0 R/W Compare Match Interrupt Enable
Enables or disables compare match interrupt (CMI)
generation when CMCNT and CMCOR values match
(CMF = 1).
0: Compare match interrupt (CMI) disabled
1: Compare match interrupt (CMI) enabled
5 to 2 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.