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Section 20 Controller Area Network
Page 1042 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit5 to 0 — Timer Prescaler (TPSC[5:0]): This control field allows the timer source clock
(4*[this module system clock]) to be divided before it is used for the timer. This function is
available only in event-trigger mode. In time trigger mode (CMAX is not 3'b111), one nominal Bit
Timing (= one bit length of CAN bus) is automatically chosen as source clock of TCNTR.
The following relationship exists between source clock period and the timer period.
Bit[5:0]: TPSC[5:0] Description
0 0 0 0 0 0 1 X Source Clock (initial value)
0 0 0 0 0 1 2 X Source Clock
0 0 0 0 1 0 3 X Source Clock
0 0 0 0 1 1 4 X Source Clock
0 0 0 1 0 0 5 X Source Clock
. . . . . . . . . . . .
. . . . . . . . . . . .
1 1 1 1 1 1 64 X Source Clock
(2) Cycle Maximum/Tx-Enable Window Register (CMAX_TEW)
This register is a 16-bit read/write register. CMAX specifies the maximum value for the cycle
counter (CCR) for TT Transmissions to set the number of basic cycles in the matrix system. When
the Cycle Counter reaches the maximum value (CCR = CMAX), after a full basic cycle, it is
cleared to zero and an interrupt is generated on IRR.10.
TEW specifies the width of Tx-Enable window.
CMAX_TEW (Address = H'084)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0000011100000000
RRRRRR/W R/W R/W RRRRR/W R/W R/W R/W
CMAX[2:0] TEW[3:0]
Bit:
Initial value:
R/W:
----- ----
Bits 15 to 11: Reserved. The written value should always be '0' and the returned value is '0'.