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Section 36 List of Registers
R01UH0134EJ0400 Rev. 4.00 Page 1845 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Section 36 List of Registers
This section gives information on the on-chip I/O registers of this LSI in the following structures.
1. Register Addresses (by functional module, in order of the corresponding section numbers)
Registers are described by functional module, in order of the corresponding section numbers.
Access to reserved addresses which are not described in this register address list is prohibited.
When registers consist of 16 or 32 bits, the addresses of the MSBs are given when big endian
mode is selected.
An asterisk (*) in the column "Access Size" indicates that the unit of access in reading differs
from that in writing for the given register. For details, see the register descriptions in the relevant
section.
2. Register Bits
Bit configurations of the registers are described in the same order as the Register Addresses
(by functional module, in order of the corresponding section numbers).
Reserved bits are indicated by "—" in the bit name.
No entry in the bit-name column indicates that the whole register is allocated as a counter or
for holding data.
3. Register States in Each Operating Mode
Register states are described in the same order as the Register Addresses (by functional
module, in order of the corresponding section numbers).
For the initial state of each bit, refer to the description of the register in the corresponding
section.
The register states described are for the basic operating modes. If there is a specific reset for an
on-chip peripheral module, refer to the section on that on-chip peripheral module.
4. Notes when Writing to the On-Chip Peripheral Modules
To access an on-chip module register, two or more peripheral module clock (P) cycles are
required. When the CPU writes data to the internal peripheral registers, the CPU performs the
succeeding instructions without waiting for the completion of writing to registers. For
example, a case is described here in which the system is transferring to the software standby
mode for power savings. To make this transition, the SLEEP instruction must be performed
after setting the STBY bit in the STBCR1 register to 1. However a dummy read of the
STBCR1 register is required before executing the SLEEP instruction. If a dummy read is
omitted, the CPU executes the SLEEP instruction before the STBY bit is set to 1, thus the
system enters sleep mode not software standby mode. A dummy read of the STBCR1 register
is indispensable to complete writing to the STBY bit. To reflect the change by internal
peripheral registers while performing the succeeding instructions, execute a dummy read of
registers to which write instruction is given and then perform the succeeding instructions.