Renesas R5S72641 Doll User Manual


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R01UH0134EJ0400 Rev. 4.00 Page 2101 of 2108
Sep 24, 2014
P
Package dimensions of this LSI ............ 2063
Page conflict ......................................... 1675
PCMCIA interface .................................. 348
Permissible signal source impedance ... 1284
Phase counting mode .............................. 529
Pin assignment of this LSI ........................ 16
Pin functions of this LSI ........................... 19
Pin states of this LSI ............................. 2047
PINT interrupts ....................................... 175
PLL circuit .............................................. 117
Power-down mode .................................. 335
Power-down modes .............................. 1769
Power-down state ..................................... 93
Power-on reset ........................................ 139
Power-on sequence ................................. 336
Power-on/power-off sequence .............. 1962
Prefetch operation
(only for operand cache) ......................... 220
Procedure register (PR) ............................. 52
Processing of analog input pins ............ 1283
Product lineup of this LSI ......................... 12
Program counter (PC) ............................... 52
Program execution state ............................ 93
PWM Modes ........................................... 524
PWM operation ..................................... 1842
Q
Quantization error ................................. 1281
R
Realtime clock ........................................ 675
Receive data sampling timing and
receive margin (asynchronous mode) ..... 772
Reconfiguration of mailbox .................. 1075
Register addresses
(by functional module, in order of
the corresponding section numbers) ..... 1846
Register bank error exception
handling .......................................... 144, 205
Register bank errors ................................ 143
Register bank exception .......................... 205
Register banks ................................... 53, 201
Register bits .......................................... 1880
Register states in each operating
mode ..................................................... 1957
Registers
ABACK0 .......................................... 1033
ABACK1 .......................................... 1033
ACKEYR ............................................ 289
ACSWR .............................................. 288
ADCSR ............................................. 1264
ADDRA to ADDRH ......................... 1263
BCR0 ................................................ 1014
BCR1 ................................................ 1012
BEMPENB ........................................ 1387
BEMPSTS ......................................... 1405
BRDYENB ....................................... 1384
BRDYSTS ........................................ 1401
BUSWAIT ........................................ 1354
CBUFCTL0....................................... 1230
CBUFCTL1....................................... 1232
CBUFCTL2....................................... 1232
CBUFCTL3....................................... 1233
CBUFST0 ......................................... 1216
CBUFST1 ......................................... 1217
CBUFST2 ......................................... 1218
CCR .................................................. 1047
CCR1 .................................................. 212
CCR2 .................................................. 214
CFIFO ............................................... 1366
CFIFOCTR ....................................... 1376
CFIFOSEL ........................................ 1368
CHCR .................................................. 385
CMAX_TEW .................................... 1042
CMCNT .............................................. 654
CMCOR .............................................. 654
CMCSR ............................................... 652