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Section 10 Direct Memory Access Controller
R01UH0134EJ0400 Rev. 4.00 Page 389 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit Bit Name
Initial
Value R/W Description
19 HE 0 R/(W)
*
3
Half-End Flag
This bit is set to 1 when the transfer count reaches half
of the DMATCR value that was specified before
transfer starts.
If DMA transfer ends because of an NMI interrupt, a
DMA address error, or clearing of the DE bit or the
DME bit in DMAOR before the transfer count reaches
half of the initial DMATCR value, the HE bit is not set
to 1. If DMA transfer ends due to an NMI interrupt, a
DMA address error, or clearing of the DE bit or the
DME bit in DMAOR after the HE bit is set to 1, the bit
remains set to 1.
To clear the HE bit, write 0 to it after HE = 1 is read.*
4
0: DMATCR > (DMATCR set before transfer starts)/2
during DMA transfer or after DMA transfer is
terminated
[Clearing condition]
Writing 0 after reading HE = 1.*
4
1: DMATCR (DMATCR set before transfer starts)/2
18 HIE 0 R/W Half-End Interrupt Enable
Specifies whether to issue an interrupt request to the
CPU when the transfer count reaches half of the
DMATCR value that was specified before transfer
starts.
When the HIE bit is set to 1, this module requests an
interrupt to the CPU when the HE bit becomes 1.
0: Disables an interrupt to be issued when DMATCR
= (DMATCR set before transfer starts)/2
1: Enables an interrupt to be issued when DMATCR
= (DMATCR set before transfer starts)/2