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Section 25 NAND Flash Memory Controller
Page 1338 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
25.5 Interrupt Sources
This module has seven interrupt sources: Status error, ready/busy timeout error, ECC error, 4-
symbol ECC pattern generation end, transfer end, FIFO0 transfer request, and FIFO1 transfer
request. Each of the interrupt sources has its corresponding interrupt flag and the interrupt can be
requested independently to the CPU if the interrupt is enabled by the interrupt enable bit. Note that
the status error, ready/busy timeout error, ECC error, and 4-symbol ECC pattern generation end,
use the common FLSTE interrupt to the CPU.
Table 25.4 NAND Flash Memory Controller Interrupt Requests
Interrupt Source Interrupt Flag Enable Bit Description Priority
FLSTE interrupt STERB STERINTE Status error High
BTOERB RBERINTE Ready/busy timeout error
ECERB ECERINTE ECC error
4ECCEND 4ECEINTE 4-symbol ECC pattern
generation end
FLTEND interrupt TREND TEINTE Transfer end
FLTRQ0 interrupt TRREQF0 TRINTE0 FIFO0 transfer request
FLTRQ1 interrupt TRREQF1 TRINTE1 FIFO1 transfer request Low
25.6 DMA Transfer Specifications
This module can request DMA transfers separately to the data area FLDTFIFO and control code
area FLECFIFO. Table 25.5 summarizes DMA transfer enable or disable states in each access
mode.
Table 25.5 DMA Transfer Specifications
Sector Access Mode Command Access Mode
FLDTFIFO DMA transfer enabled DMA transfer enabled
FLECFIFO DMA transfer enabled DMA transfer disabled
For details on settings of the direct memory access controller, see section 10, Direct Memory
Access Controller.