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Section 18 Serial Sound Interface
Page 934 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
(1) Reception Using Direct Memory Access Controller
Yes
No
No
Yes
Yes
No
RUIEN = 1, ROIEN = 1, RIE = 1,
REN = 1
REN = 0,
RUIEN = 0, ROIEN = 0,
IIEN = 1, RIE = 0
Start
Release from reset,
set SSICR configuration bits.
Set up the direct memory
access controller.
Enable the direct memory
access controller.
Enable error interrupts
and receive interrupts,
then enable reception.
Wait for an interrupt.
Error interrupt?
End of DMA transfer?
More data to be received?
Disable receive operation,
disable an error interrupt,
enable an idle interrupt.
Wait for an idle interrupt
from this module
End*
Define SCKD, SWSD, MUEN,
DEL, PDTA, SDTA, SPDP,
SWSP, SCKP, SWL, DWL,
CHNL
Note: * If an error interrupt (underflow/overflow) occurs,
go back to the start in the flowchart again.
Figure 18.22 Reception Using Direct Memory Access Controller