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Section 26 USB 2.0 Host/Function Module
R01UH0134EJ0400 Rev. 4.00 Page 1481 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
(1) BRDY Interrupt
The BRDY interrupt is generated when either of the host controller function or function controller
function is selected. The following shows the conditions under which this module sets 1 to a
corresponding bit in BRDYSTS. Under this condition, this module generates BRDY interrupt, if
the PIPEBRDYE bit in BRDYENB that corresponds to the pipe to 1 and the BRDYE bit in
INTENB0 have been set to 1.
The conditions for generating and clearing the BRDY interrupt depend on the settings of the
BRDYM bit and BFRE bit for the pertinent pipe as described below.
(a) When the BRDYM bit is 0 and BFRE bit is 0
With these settings, the BRDY interrupt indicates that the FIFO port is accessible.
On any of the following conditions, this module generates the internal BRDY interrupt request
trigger and sets 1 to the PIPEBRDY bit corresponding to the pertinent pipe.
(i) For the pipe in the transmitting direction:
When the DIR bit is changed from 0 to 1.
When packet transmission is completed using the pertinent pipe when write-access from
the CPU to the FIFO buffer for the pertinent pipe is disabled (when the BSTS bit is read as
0).
In continuous transmission/reception mode, the request trigger is generated on completion
of transmitting data of one plane of the FIFO buffer.
When one FIFO buffer is empty on completion of writing data to the other FIFO buffer in
double buffer mode.
The request trigger is not generated until completion of writing data to the currently-written
FIFO buffer plane even if transmission to the other FIFO buffer is completed.
When the hardware flushes the buffer of the pipe for isochronous transfers.
When 1 is written to the ACLRM bit, which causes the FIFO buffer to make transition
from the write-disabled to write-enabled state.
The request trigger is not generated for the DCP (that is, during data transmission for control
transfers).