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Section 33 Power-Down Modes
R01UH0134EJ0400 Rev. 4.00 Page 1803 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
33.2.19 Deep Standby Cancel Source Flag Register (DSFR)
DSFR is a 16-bit readable/writable register composed of two types of bits. One is the flag that
confirms which source canceled deep standby mode. The other is the bit that releases the state of
pins after canceling deep standby mode. When deep standby mode is canceled by an interrupt
(NMI, realtime clock alarm interrupt, or change on the pins for canceling) and changes on the pins
for canceling, this register retains the previous data although power-on reset exception handling is
executed. When deep standby mode is canceled by a power-on reset, this register is initialized to
H'0000.
All flags must be cleared immediately before transition to deep standby mode.
Note: When writing to this register, see section 33.4, Usage Notes.
1514131211109876543210
Bit:
Initial value:
R/W:
0000000000000000
R/(W)*
Note: * Only 0 can be written after reading 1 to clear the flag.
R R R R R/(W)*R/(W)*R/(W)* R R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*
IO
KEEP
- - - - PG11F PG10F NMIF -
RTC
ARF
PC8F PC7F PC6F PC5F PJ3F PJ1F
Bit Bit Name
Initial
Value R/W Description
15 IOKEEP 0 R/(W)* Release of Pin State Retention
Releases the retention of the pin state after canceling
deep standby mode
0: Pin state not retained
[Clearing condition]
Writing 0 after reading 1
1: Pin state retained
[Setting condition]
When deep standby mode is entered
14 to 11 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
10 PG11F 0 R/(W)* PG11 Flag
0: No change on the PG11 pin
1: Change on the PG11 pin
Note: For 1-Mbyte version, this bit is reserved and
always read as 0. The write value should
always be 0.