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Section 6 Exception Handling
R01UH0134EJ0400 Rev. 4.00 Page 137 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
6.2 Resets
6.2.1 Input/Output Pins
Table 6.5 shows the pin configuration.
Table 6.5 Pin Configuration
Pin Name Symbol I/O Function
Power-on reset RES Input When this pin is driven low, this LSI shifts to the power-
on reset processing
6.2.2 Types of Reset
A reset is the highest-priority exception handling source. There are two kinds of reset, power-on
and manual. As shown in table 6.6, the CPU state is initialized in both a power-on reset and a
manual reset. The FPU state is initialized by a power-on reset, but not by a manual reset. On-chip
peripheral module registers except a few registers are also initialized by a power-on reset, but not
by a manual reset.
Table 6.6 Reset States
Type Conditions for Transition to Reset State Internal States
RES
User Debugging
Interface Command
Watchdog
Timer
Overflow
CPU
Other
Modules
On-Chip
High-Speed
RAM
On-Chip Large-
Capacity RAM
(Excluding
On-Chip Data
Retention RAM)
On-Chip
Data
Retention
RAM
Power-
on reset
Low Initialized Initialized Initialized or
Retained
contents*
2
Initialized or
Retained
contents*
3
Initialized or
Retained
contents*
4
, *
5
High User debugging
interface reset assert
command is set
Initialized Initialized Initialized or
Retained
contents*
2
Initialized or
Retained
contents*
3
Initialized or
Retained
contents*
4
High Command other than
user debugging
interface reset assert is
set
Power-on
reset
Initialized *
1
Initialized or
Retained
contents*
2
Initialized or
Retained
contents*
3
Initialized or
Retained
contents*
4