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Page 2074 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
Item Page Revision (See Manual for Details)
16.3.9 Data Control
Register (SPDCR)
795 Table amended
Bit Bit Name
Initial
Value
R/W Description
7 TXDMY 0 R/W Dummy Data Transmission Enable
...
Specifically, if there is no transmit data in the
transmit buffer and this bit is set to 1, dummy data is
transferred to the shift register.
0: Disables dummy data transmission.
1: Enables dummy data transmission.
Note: This bit is valid only in the master mode.
The
dummy data is undefined.
16.4.3 System
Configuration Example
(3) Master/Multi-Slave (with
This LSI Acting as Slave)
Figure 16.5 Master/Multi-
Slave Configuration Example
(This LSI = Slave)
812 Figure amended
This LSI (slave Y)
RSPCK
MOSI
MISO
SSL
16.4.5 Data Format
(2) MSB First Transfer (16-
Bit Data)
Figure 16.9 MSB First
Transfer (16-Bit Data)
818 Figure amended
51 tiB13 tiB
Bit 15
Bit 0
Bit 31 Bit 0
Transfer end
T15 T14 T13 T12 T11 T03 T02 T01 T00 T15 T14 T13 T12 T11 T03 T02 T01 T00
Shift register
Shift register
T15 T14 T13 T12 T11 T03 T02 T01 T00 R15 R14 R13 R12 R11 R03 R02 R01 R00
Output
Input
(3) MSB First Transfer (8-Bit
Data)
Figure 16.10 MSB First
Transfer (8-Bit Data)
820 Figure amended
Bit 7
0 tiB7 tiB13 tiB
Copy
Transfer end
Transfer start
Bit 0
T07 T06 T05 T04
T03
T02 T01 T00
T07 T06 T05 T00 T07 T06 T01 T00 T00 T01 T00 T07 T06 T11 T01 T00
Shift register
Shift register
Transmit buffer (SPTX)
T07 T06 T05 T04 T03 T02 T01 T00 R07 R06 R05 R04 R03 R02 R01 R00
Input
Output
0 tiB7 tiB13 tiB