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Section 37 Electrical Characteristics
R01UH0134EJ0400 Rev. 4.00 Page 2005 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Notes: 1. An address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn and TENDn is when active low is specified.
Tc2 Tc3 Tc4TrTpwTp Tc1
t
AD1
t
CSD1
t
AD1
t
AD1
t
AD1
t
RWD1
t
RWD1
t
RWD1
t
RWD1
t
CSD1
t
RASD1
t
RASD1
t
RASD1
t
RASD1
t
AD1
t
AD1
t
AD1
t
AD1
CKIO
A25 to A0
CSn
RD/WR
A12/A11
*
1
D15 to D0
RAS
WRIT command
Row address
t
AD1
t
AD1
Column address
t
CASD1
t
CASD1
CAS
t
BSD
t
BSD
(High)
BS
CKE
t
DQMD1
t
DQMD1
DQMxx
t
DACD
t
DACD
DACKn
TENDn
*
2
t
WDH2
t
WDD2
t
WDH2
t
WDD2
Figure 37.30 Synchronous DRAM Burst Write Bus Cycle (Four Write Cycles)
(Bank Active Mode: PRE + ACT + WRITE Commands, Different Row Addresses,
WTRCD = 0 Cycle, TRWL = 0 Cycle)