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Section 32 General Purpose I/O Ports
Page 1718 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
(4) Port D Control Register 0 (PDCR0)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0/1 0 0 0 0/1 0 0 0 0/1 0 0 0 0/1
R R R/W R/W R R R/W R/W R R R/W R/W R R R/W R/W
---
PD2MD[1:0] PD1MD[1:0] PD0MD[1:0]PD3MD[1:0]
-- ---
Bit:
Initial value:
R/W:
Bit Bit Name Initial Value R/W Description
15, 14 All 0 R Reserved
These bits are always read as 0. The write
value should always be 0.
13, 12 PD3MD[1:0] 00/01 R/W PD3 Mode
Select the function of the PD3.
Boot mode 0
00: Setting prohibited
01: D3 (initial value)
10: Setting prohibited
11: Setting prohibited
Boot mode 1 to 3
00: PD3 (initial value)
01: D3
10: PWM1D
11: Setting prohibited
11, 10 All 0 R Reserved
These bits are always read as 0. The write
value should always be 0.
9, 8 PD2MD[1:0] 00/01 R/W PD2 Mode
Select the function of the PD2.
Boot mode 0
00: Setting prohibited
01: D2 (initial value)
10: Setting prohibited
11: Setting prohibited
Boot mode 1 to 3
00: PD2 (initial value)
01: D2
10: PWM1C
11: Setting prohibited
7, 6 All 0 R Reserved
These bits are always read as 0. The write
value should always be 0.