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Section 26 USB 2.0 Host/Function Module
Page 1356 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
Table 26.5 USB Data Bus Line Status
LNST[1] LNST[0]
During Low-Speed
Operation (only when
Host Controller
Function is Selected)
During Full-
Speed
Operation
During High-
Speed
Operation
During Chirp
Operation
0 0 SE0 SE0 Squelch Squelch
0 1 K state J state Unsquelch Chirp J
1 0 J state K state Invalid Chirp K
1 1 SE1 SE1 Invalid Invalid
[Legend]
Chirp: The reset handshake protocol (RHSP) is being executed in high-speed operation
enabled state (the HSE bit in SYSCFG is set to 1).
Squelch: SE0 or idle state
Unsquelch: High-speed J state or high-speed K state
Chirp J: Chirp J state
Chirp K: Chirp K state
26.3.4 Device State Control Register (DVSTCTR)
DVSTCTR is a register that controls and confirms the state of the USB data bus.
This register is initialized by a power-on reset. After a USB bus reset, only the WKUP bit is
initialized.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit:
Initial value:
R/W:
0000000000000000
RRRRRRRR/W* R/W R/W R/W R/W R R R R
— — — — — — — WKUP RWUPEUSBRSTRESUME UACT —
RHST[2:0]
Bit Bit Name
Initial
Value R/W Description
15 to 9 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.