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Section 7 Interrupt Controller
R01UH0134EJ0400 Rev. 4.00 Page 205 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
7.8.4 Register Bank Exception
There are two register bank exceptions (register bank errors): register bank overflow and register
bank underflow.
(1) Register Bank Overflow
This exception occurs if, after data has been saved to all of the register banks, an interrupt for
which register bank use is allowed is accepted by the CPU, and the BOVE bit in the bank number
register (IBNR) is set to 1. In this case, the bank number bit (BN) value in the bank number
register (IBNR) remains set to the bank count of 15 and saving is not performed to the register
bank.
(2) Register Bank Underflow
This exception occurs if the RESBANK (restore from register bank) instruction is executed when
no data has been saved to the register banks. In this case, the values of R0 to R14, GBR, MACH,
MACL, and PR do not change. In addition, the bank number bit (BN) value in the bank number
register (IBNR) remains set to 0.
7.8.5 Register Bank Error Exception Handling
When a register bank error occurs, register bank error exception handling starts. When this
happens, the CPU operates as follows:
1. The exception service routine start address which corresponds to the register bank error that
occurred is fetched from the exception handling vector table.
2. The status register (SR) is saved to the stack.
3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the
instruction to be executed after the last executed instruction for a register bank overflow, and
the start address of the executed RESBANK instruction for a register bank underflow. To
prevent multiple interrupts from occurring at a register bank overflow, the interrupt priority
level that caused the register bank overflow is written to the interrupt mask level bits (I3 to I0)
of the status register (SR).
4. Program execution starts from the exception service routine start address.